A random access memory (RAM) is a memory capable of being read and written, and may access each memory cell according to an instruction randomly and individually in a fixed access time and regardless of an address of the memory cell. MOS-type memories may be divided into two types according to the means of storing information, which are dynamic random access memories (DRAMs) and static random access memories (SRAMs).
A DRAM is a common system memory due to its density and speed. The memory cell of the DRAM is a capacitor including electric charges leaked with time, leading to that data in the DRAM is lost. The DRAM may keep the data for a short time. In order to solve this problem, the memory cell of the DRAM is required to be refreshed at intervals. If the memory cell is not refreshed, data stored in the memory cell may be lost. The refresh frequency of the DRAM depends on a manufacturing technology and a design of the memory cell. The refresh frequency of the DRAM may affect the performance and power consumption. A disadvantage of the DRAM is that a leakage of electricity at a gate electrode of a memory transistor increases obviously as a size of an integrated circuit decreases, and the stored data may be lost very soon.
A memory circuit of a SRAM is based on a bistable trigger. The state of the SRAM is stable and data is lost as long as the power does not disenergized. The advantages of the SRAM are that it is unnecessary to refresh the SRAM, a control circuit of the SRAM is simple. The disadvantage of the SRAM is that the integration level is low, such that the size of the SRAM is bigger than that of the DRAM with the same capacity and that the power consumption is high. Thus, the SRAM may occupy a part of areas of a main board.
As the development of the nuclear power technology and the space technology, more and more electronic devices are applied in various radiation environments. As the increased demand for the system performance in the space application, the decreased size of the device and the improvement of the technology, the sensitivity of a semiconductor to the space radiation becomes high, and the influence of the single event effect (SEE) is extended. The SRAM is widely used in various military and space systems. The bistable circuit in the SRAM is particularly sensitive to the single event upset effect, resulting in errors occurring in the data and instructions stored in the SRAM or even a failure occurring in the space system. Thus, it is necessary to harden the SRAM.
The single event upset refers that after a single particle comes into a well region or a gate capacitance region of a device, electrons of an electron hole pair generated in an ionization trajectory of the single particle are collected at positive voltage area and the electron hole flows to a low potential direction, and if the well region (or the gate capacitance region) has been filled with electrons the state of the device does not change, else if the well region (or the gate capacitance region) is partially filled with the electrons generated according to the single event upset, and the state changes after enough electrons are collected.
With regard to a CMOS SRAM memory cell with standard six transistors, as shown in FIG. 1, generally, the depletion layer of a reverse biased PN junction at a drain area of a MOS transistor which is in an OFF state is a sensitive area of the single event upset. Assuming that Q=“1” and Qn=“0”, a “1” is stored in the memory cell, transistors N2 and P1 are in an ON state and transistors N1 and P2 are in an OFF state. At this time, a high-energy particle comes into the drain area of the transistor N1 which is in an OFF state. The transient current resulted from the high-energy particle pulls the level of the drain electrode of the transistor N1 (i.e. the level at the node Q) down to a low level, and the transistor P1 is still in an ON state. And then, a capacitance at the node Q is charged by a power supply VDDI, and the memory cell is in an unstable state. Meanwhile, since the level at the node Q is pulled down to the low level by the transient current, the transistor N2 is turned off, the transistor P2 is turned on and the level at the node Qn is pulled up. And then the high level at the node Qn results in the transistor N1 being turned on and the transistor P2 being turned off, thus the “1” stored in the memory cell is changed to a “0”. Therefore, after the high-energy particle comes into the sensitive area of the SRAM cell, if a recovery time tr is less than a feedback time tf, the high-energy particle does not result in the single event upset, if the recovery time tr is greater than the feedback time tf, the transient current due to the high-energy particle results in the single event upset.
At present, there are many methods to solve the single event upset, including a resistance harden method, a technology harden method, a system error correction harden method, a circuit design harden method, etc. The resistance harden method is restricted in practical practice because that the technology of the resistance is required to be introduced, it is difficult to integrate and the effect cannot be guaranteed in a severe environment. The technology harden method (such as a SOI technology, an extension technology, etc.) may improve the capability of resisting the single event upset of the memory cell by decreasing the charges collected at the sensitive area. However, the disadvantage of the technology harden method is that its cost is high and it is not compatible with a CMOS technology. The system error correction harden method may solve errors resulted from the SRAM memory cell due to the single event effect in a peripheral circuit, such that the accuracy of the system is guaranteed. But the overhead of the error correction circuit increases, the refresh frequency of the error correction increases and the performance of the memory is degraded, since the line width is reduced to a scale of nanometer, the size of the SRAM memory cell constantly decreases and the error rate increases sharply. The circuit design harden method may obtain a good capability of resisting the radiations by designing a complex memory cell using the ideas of “redundance” and “recovery”. Conventional memory cells include 6T2C, 6T2C2R, 8T, 10T, DICE, etc. But a peripheral circuit in a conventional circuit design harden method is complex and a size of the memory cell is huge, such that it is difficult to apply the conventional circuit design harden method in a node with a size greater than 0.18 nanometer.